first public release
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61
dd_fd_prefix_test.go
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61
dd_fd_prefix_test.go
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package z80
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import "testing"
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// Test LD r,(IX+d) and LD (IX+d),r timing and behavior.
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func TestIndexedLoadsIX(t *testing.T) {
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cpu, mem, _ := testCPU()
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cpu.IX = 0x3000
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mem.WriteByte(0x3005, 0xAB)
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// DD 46 05 = LD B,(IX+5)
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loadProgram(cpu, mem, 0x0000, 0xDD, 0x46, 0x05)
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c := mustStep(t, cpu)
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assertEq(t, cpu.B, byte(0xAB), "LD B,(IX+5)")
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assertEq(t, c, 19, "cycles for LD r,(IX+d)")
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// DD 70 05 = LD (IX+5),B
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loadProgram(cpu, mem, cpu.PC, 0xDD, 0x70, 0x05)
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c = mustStep(t, cpu)
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assertEq(t, mem.ReadByte(0x3005), cpu.B, "LD (IX+5),B")
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assertEq(t, c, 19, "cycles for LD (IX+d),r")
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}
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// Undocumented IXH/IXL access: LD IXH,n; LD IXL,n; ADD A,IXH; XOR IXL
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func TestIXHIXL_Undocumented(t *testing.T) {
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cpu, mem, _ := testCPU()
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// DD 26 12 = LD IXH,12; DD 2E 34 = LD IXL,34
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// DD 84 = ADD A,IXH (ADD A,H with DD prefix)
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// DD AE = XOR (HL)?? No, for XOR r it's 0xAE for (HL); use DD A5 = AND L ?
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// We'll do: LD A,0x01; DD 84 (ADD A,IXH) -> 0x13; DD B5 isn't valid; use DD A5 for AND IXL via "AND L" with DD -> IXL.
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loadProgram(cpu, mem, 0x0000,
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0xDD, 0x26, 0x12,
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0xDD, 0x2E, 0x34,
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0x3E, 0x01,
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0xDD, 0x84, // ADD A,IXH
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0xDD, 0xA5, // AND IXL (AND L with DD prefix)
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)
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mustStep(t, cpu) // LD IXH,12
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mustStep(t, cpu) // LD IXL,34
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mustStep(t, cpu) // LD A,01
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mustStep(t, cpu) // ADD A,IXH -> 0x13
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assertEq(t, cpu.A, byte(0x13), "ADD A,IXH")
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mustStep(t, cpu) // AND IXL (0x34) -> 0x10
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assertEq(t, cpu.A, byte(0x10), "AND IXL")
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// XY flags come from A after logical ops per implementation
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assertFlag(t, cpu, FLAG_X, (cpu.A&FLAG_X) != 0, "X from A after AND")
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assertFlag(t, cpu, FLAG_Y, (cpu.A&FLAG_Y) != 0, "Y from A after AND")
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}
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// IY mirrors IX tests.
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func TestIndexedLoadsIY(t *testing.T) {
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cpu, mem, _ := testCPU()
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cpu.IY = 0x4000
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mem.WriteByte(0x4002, 0x55)
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// FD 4E 02 = LD C,(IY+2)
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loadProgram(cpu, mem, 0x0000, 0xFD, 0x4E, 0x02)
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c := mustStep(t, cpu)
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assertEq(t, cpu.C, byte(0x55), "LD C,(IY+2)")
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assertEq(t, c, 19, "cycles for LD r,(IY+d)")
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}
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